IBM Systems and Technology Group Markus Bühler Jeanne Bickford Jason Hibbeler Jürgen Koehl DATE 2006
Outline Catastrophic Failures Defect Mechanisms State of the Art Novel Techniques Conclusion 2
Catastrophic Failures 3
Defect Mechanisms: Random Defects caused by particles shorts opens quantitative prediction by Critical Area Analysis (CAA) given defect size x x calculate area where a defect of size x is catastrophic CA sum CA over all shapes of design weighted integrate over all defect sizes: p(x) 4
Defect Mechanisms: Systematic Failures Lithography issues Things don't print as drawn Design Analysis Litho-Simulation Expert system approach point to hot spots on design no quantitative yield prediction Many other issues (e.g. with CMP) 5
State of the Art Wire Spreading Redundant Vias Driven by short sensitivity on aluminum Wire spreading increases net length higher sensitivity to opens always a good thing slightly higher sensitivity to shorts 6
New Techniques for Copper Changing fail mechanisms Aluminum: shorts/opens = 3:1 Copper: shorts/opens = 1:1 Higher sensitivity to opens Non-Tree Routing (Kang, 2004) Spreading + Wire Widening Both approaches have significant timing impact 7
Local Loops Not every via can be made redundant Design 1 130 nm Design 2 130 nm Design 3 90 nm % of redundant vias 88.5% 77.5% 68% More redundancy: local loops 8
Advantages of Local Loops Simple extension of redundant via approach Can be implemented w/o wrong way wiring Less fault correlation due to higher distance Critical area reduction is higher than with redundant vias Minimal timing impact CAA: 5 Experiments Single via only Redundant via only Redundant via + local loops Local loops only Local loops + redundant vias Relative Critical Area 1,6 1,4 1,2 1,0 0,8 0,6 0,4 0,2 0,0 Single via Red via Red via + Loop Loop Loop + red via Metal Open Via Open Metal Short 9
Global Loops Kang 2004: augment existing wiring Traveling Salesman approach* Pins overhead* protected Pins overhead* protected 5 33% 54% 10 38% 100% 10 50 17% 4% 47% 36% 20 100 27% 15% 100% 100% 10 * compared to minimum Steiner tree * compared to minimum spanning tree *P. Panitz, M. Olbrich, IMS, U. Hannover
Global Loops cont. Efficiency Accumulated Netlength over Pincount Tree links TSM 120% 100% 80% 60% Nets Net Length pin limit red. wiring overhead 5 17% 11% 10 16% 6% 40% 20% 0% 1 2 3 4 5 6 7 8 9 10 Sinks Comparison is not fair! Timing issues TSM in general both in case of fault Still some research required! 11
CAA on Library Elements CAA has long runtimes CAA gives global yield number no hints where problems are late feedback limited use for design tools Critical area library characterization perform CAA on each library element characterize possible cell interaction calculate fail probability for each cell Possible short in adjacent cells Perimeter fail probability enables early yield estimation tools guidance 12
Feature Variation Relative feature variation increases with shrinking technology - dopant density - line width Features vary independently - Example: wire width variation causes hardware failure T clock = 2ns t d =1.9ns M4 M5 AT1 AT2 budget slack slow slow 1.0 1.0 2.0 0.1 fast fast 0.8 0.8 2.0 0.1 fast slow 0.8 1.0 2.2 0.3 Variation Aware Timing slow fast 1.0 0.8 1.8-0.1 Statistical Timing 13
Conclusion Design for yield is design for low cost and quality Traditional techniques are not sufficient Multiple aspects - redundancy - defect robustness - variation robustness DfY doesn't come for free - timing issues - wiring congestion increase - noise issues There is a lot to be gained but also a lot to do! 14