LX5380 RISC-DSP for New Internet Applications. Pat Hays, Chris Hanna, Jonah Probell October 25, 2001

Transkript

1 LX5380 RISC-DSP for New Internet Applications Pat Hays, Chris Hanna, Jonah Probell October 25, 2001

2 Outline Benefits of RISC-DSP Cores The LX5380 RISC-DSP Example: 3G Wireless Handset Example: VoIP Gateway Roadmap Summary

3 Benefits of RISC-DSP Cores Cost and Power-Sensitive Designs RISC UNUSED USED DSP UNUSED USED RISC CORE DSP CORE UNIT N (UNUSED) PERIPHERALS I/O UNIT (USED)

4 Benefits of RISC-DSP Cores Cost and Power-Sensitive Designs USED USED RISC CORE DSP CORE Core Benefit PERIPHERALS I/O UNIT (USED) Tailor resources

5 Benefits of RISC-DSP Cores Cost and Power-Sensitive Designs USED RISC-DSP CORE I/O UNIT (USED) PERIPHERALS Core Benefit RISC-DSP Benefit New Requirement Tailor resources Single processor Memory Management

6 Benefits of RISC-DSP Cores High-Performance, Multi-Channel Designs RISC-DSP CORE RISC-DSP CORE RISC-DSP CORE RISC-DSP CORE RISC-DSP CORE I/O UNIT Core Benefit RISC-DSP Benefit New Requirement On-chip Multi-Processing Excellent S/W Tools Higher Performance

7 Evolution of the LX5380 RISC-DSP Start with a 32-bit LX4180 RISC (1998) CPU IMEM ICACHE CUSTOMER COPROCESSORS CP0 INST ADDR, TRAPS, INT REG FILE R0 R31 3-PORT ALU INTERFACE COP INTERFACE INSTRUCTION BUS DATA BUS SYS BUS I/F ADDRESS DATA INTERFACE DMEM DCACHE EJTAG PROBE Add a 2 nd execution pipeline, dual MAC and DSP instructions Provided by Lexra

8 Evolution of the LX5380 RISC-DSP LX5280: Superscalar RISC-DSP (1999) CPU IMEM ICACHE CUSTOMER COPROCESSORS CP0 INST ADDR, TRAPS, INT ALU REG FILE R0 R31 8-PORT ALU INTERFACE COP INTERFACE INSTRUCTION BUS DATA BUS SYS BUS I/F ADDRESS DATA DUAL MAC LOAD STORE UNIT INTERFACE DMEM DCACHE EJTAG PROBE A single pipeline implementation for lower cost, lower power Provided by Lexra

9 Evolution of the LX5380 RISC-DSP LX5180: Low-cost RISC-DSP (2000) CPU IMEM ICACHE CUSTOMER COPROCESSORS CP0 INST ADDR, TRAPS, INT REG FILE R0 R31 4-PORT ALU INTERFACE COP INTERFACE INSTRUCTION BUS DATA BUS SYS BUS I/F ADDRESS DATA DUAL MAC LOAD STORE UNIT INTERFACE DMEM DCACHE EJTAG PROBE Add new RISC and new DSP features Provided by Lexra

10 Evolution of the LX5380 RISC-DSP LX5380 RISC-DSP (2001) CPU 7-STAGE PIPELINE IMEM ICACHE CUSTOMER COPROCESSORS CP0 INST ADDR, TRAPS, INT REG FILE R0 R31 6-PORT ALU MMU INTERFACE COP INTERFACE INSTRUCTION BUS DATA BUS SYS BUS I/F ADDRESS DATA RADIAX-2 INSTRUCTIONS DUAL MAC LOAD STORE UNIT INTERFACE DMEM DCACHE BLOCK MOVE CONTROLLER EJTAG PROBE Provided by Lexra New to the LX5380

11 Summary of New LX5380 Features NEW FEATURE MANAGEMENT UNIT IMPROVED CACHES (2-WAY SET, WRITE BACK) 7-STAGE PIPELINE 64-BIT SYSTEM BUS BLOCK MOVE CONTROLLER 20 NEW RADIAX-2 INSTRUCTIONS BIT-FIELD OPERATIONS 32-BIT DSP OPERATIONS PERFORMANCE OPTIMIZATIONS RISC BENEFIT O/S PROTECTION FOR 3 RD PARTY CODE REDUCED SYSTEM BUS ACTIVITY FASTER CLOCK FASTER DATA TRANSFER DSP BENEFIT FASTER CLOCK FASTER DATA TRANSFER BACKGROUND TRANSFER OF BUFFERED SAMPLES BETTER 32-BIT ARITHMETIC FOR AUDIO EFFICIENT PACKET PROCESSING IMPROVED COMPILATION

12 LX Stage Pipeline Positive-edge only. Full-cycle for memory. 5-Stage RISC Pipeline Instruction Source Fetch Execution Memory Write Back 7-Stage LX5380 Pipeline I Fetch Decode Source Fetch Execution Access Memory Write Back RAM Access RAM Access Instruction memory access Instruction transfer and decode, Instruction address computation Register file access and forwarding ALU ops, Data address computation Data memory access Data memory transfer and alignment Register file update

13 LX5380 Processor Specifications Synthesized RTL (0.13 µm LV) Performance measures: Clock (wc process, wc conditions) 360 MHz Clock (typ process, wc conditions) 420 MHz Peak 16-bit operations 2 MACs/cycle A(N) B(N), 32-bit precision 2N cycles Power dissipation (wc conditions) 0.2 mw/mhz Die area (no memory, MMU, BMC) 1.9 mm 2

14 Example: 3G Wireless Handset Requirements Ultra low-cost, low-power Hardware for well-defined functions, but Flexible platform for new features Demands programmability Open platform Operating systems: EPOC, Windows CE, Linux, OSE, JAVA

15 Example: 3G Wireless Handset LX5380 Processing Tasks PROCESSING TASKS DSP TASKS CDMA EVRC SPEECH CODEC AUTOMATIC GAIN CONTROL AND MIC ARRAY ACOUSTIC ECHO CANCELLER (32 ms WINDOW) MP3 DECODE AUDIO MIXER MPEG-4 QCIF DECODE (15 FPS) MPEG-4 QCIF ENCODE (15 FPS) SPEEECH RECOGNIZER (LIMITED VOCABULARY) COMMUNICATIONS PROTOCOLS (384 KBPS) QVGA RENDERING (15 FPS) I/O RTOS AND JAVA VIRTUAL MACHINE TOTAL RISC-DSP WORKLOAD 38 MHz 7 MHz 10 MHz 32 MHz 2 MHz 16 MHz 62 MHz N/A 10 MHz 16 MHz 2 MHz 5 MHz 200 MHz

16 Example: 3G Wireless Handset Block Diagram of LX5380 Solution RF FRONT END BASE- BAND DAC / ADC VIDEO ADAPTER, KEYPAD DISPLAY I/F DISPLAY / KEYPAD LX5380 RISC DSP SUBSYSTEM AUDIO DAC / ADC SPEAKER MICROPHONE WCDMA MODEM USB I /F SDRAM SDRAM CONTROL B U S I/F FLASH SIM CARD

17 Example: VoIP Gateway Requirements Phone-to-network connectivity Reduce system and customer cost Enable new services. E.g. follow-me Extensive RISC and DSP program tasks Scalability SoHo 4 24 channels Enterprise hundreds of channels Central Office thousands channels

18 Example: VoIP Gateway LX5380 Processing Tasks PROCESSING TASKS SIGNAL PROCESSING CODECS (G.711, G.726, G.723.1, G728, G729A) ECHO CANCELLATION (G.165, G.168, 32ms TAIL) DTMF DETECT/GEN VOICE ACTIVITY DETECT (VAD), COMFORT NOISE GEN (CNG), SIGNAL CLASSIFICATION PACKET PROCESSING ENCAPSULATE/ DE-ENCAPSULATE, ADAPTIVE JITTER BUFFER, LOST PACKET COMPENSATION TELEPHONY SIGNALING/CONTROL CALL PROCESSING, ADDRESSING, H.323 PROTOCOLS NETWORK PROTOCOL TCP/IP STACK NETWORK MANAGEMENT AND APPLICATION LAYER SNMP (MIB) FIREWALL, SIP, HTTP SERVER, USER I/F I/O RTOS TOTAL RISC WORKLOAD (24 CHANNELS) 26 MHz 30 MHz 100 MHz (AVAILABLE) 2 MHz 2 MHz 160 MHz DSP WORKLOAD (8 CHANNELS) 156 MHz (WORST CASE) 58 MHz 18 MHz 22 MHz 10 MHz 1 MHz 1 MHz 266 MHz

19 Example: VoIP Gateway The LX5380 SoHo Solution PSTN CONNECTIONS DSP 1 DSP 2 DSP 3 PCM 1 8 SDRAM 8 MB LX5380 (DSP TASKS) SDRAM CONTROL LX5380 (DSP TASKS) LX5380 (RISC TASKS) RISC LX5380 (DSP TASKS) 10/100 ETHERNET MAC UNIT B U S I/F PCM 2 PCM 3 EPROM 2 MB 8 8 LOCAL AREA NETWORK 24 channels. Scales to support 256 channels

20 LX5xxx RISC-DSP Roadmap SUSTAINED MMACs 1200 LX DUAL-ISSUE SUPERSCALAR LX5480 LX LX5280 LX5380 SINGLE PIPELINE LX st GEN (0.18 µm) 2nd GEN (0.13 µm) 3rd GEN (0.11 µm)

21 Summary New internet-enabled applications demand a convergence of RISC and DSP functionality RISC-DSP cores achieve Low cost, low-power in single core applications High performance in multi-channel applications The LX5380 extends both the RISC and DSP benefits of Lexra s RISC-DSP product line