F5 IN2060 2018 Digitale byggeblokker Yngve Hafting, yngveha@ifi.uio.no
Kort om emnet Formål Emnet tar for seg prinsipper i digital design, som kombinatorisk og sekvensiell logikk, tilstandsmaskiner og digitale byggeblokker, og bygger på dette for å introdusere prosessorarkitekturer, pipelining, cache, og grensesnittet mellom maskinvare og programkode. Hva lærer du? Etter å ha tatt IN2060 har du: kunnskaper om hvordan en datamaskin er satt sammen og fungerer, fra logiske porter til prosessor kunnskaper om grensesnittet mellom maskinvare og programvare lært å kunne analysere og konstruere digitale kretser Delmål Forstå hvordan oppbygningen av kretser kan føre til tidsforsinkelser (propagation delay) Kjenne til og kunne beskrive virkemåte til noen digitale byggeblokker (som er vesentlige innen prosessorarkitekturer og programmerbar logikk): Addere ALU Shiftregistre Tellere Minneelementer Programmerbar logikk Hvordan? Forelesning + selvstudium: Aritmetiske kretser Addere, ALU, Shiftregistere Sekvensielle byggeblokker Tellere Minne RAM ROM Programmerbar logikk ROM logikk (LUTer) PLA Logiske blokker Ukeoppgaver Øvelse i å tolke og beskrive virkemåte til digitale byggeblokker i form av skjema, HDL og tekst. Oblig Kjennskap til MAC algoritme og bli kjent med dens oppbygning Gruppetimer HDL eksempler, digitale byggeblokker 3 Gjennomgang av oppgaver
Introduction Digital building blocks: Gates, multiplexers, decoders, registers, arithmetic circuits, counters, memory arrays, logic arrays Building blocks demonstrate hierarchy, modularity, and regularity: Hierarchy of simpler components Well-defined interfaces and functions Regular structure easily extends to different sizes ENB B A D Q CLK Encode 1 0 Decode Will use these building blocks in Chapter 7 to build microprocessor Counter + - ALU Chapter 5 <4>
1-Bit Adders Half Adder Full Adder A B Cin A B A B C out + S C out + S C in VHDL: A B 0 0 0 1 1 0 1 1 S = A B C out = AB C out S 0 0 C in A B 0 1 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 C out 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 -- Half adder: S <= A xor B; Cout <= A and B; S Cout -- Full adder: S <= A xor B xor Cin; Cout <= ((A xor B) and Cin) or (A and B) = XOR S = A B C in C out = AB + AC in + BC in Merk: implementasjon på transistornivå blir ikke nødvendigvis som vist på figur Chapter 5 <5>
Multibit Adders (CPAs) Types of carry propagate adders (CPAs): Ripple-carry (slow) Carry-lookahead (fast) Prefix (faster) Carry-lookahead and prefix adders faster for large adders but require more hardware Symbol A N B N C out + S N C in Chapter 5 <6>
Ripple-Carry Adder Chain 1-bit adders together Carry ripples through entire chain Disadvantage: slow A 31 B 31 A 30 B 30 A 1 B 1 A 0 B 0 C out + C + 30 C 29 C + 1 C + 0 C in S 31 S 30 S 1 S 0 Chapter 5 <7>
Ripple-Carry Adder Delay A B Cin A B C out + C in t ripple = Nt FA S Cout S where t FA is the delay of a 1-bit full adder, N is the number of bits (width) C out A + S B C in A B Cin S Cout Chapter 5 <8>
Carry-Lookahead Adder Kan vi øke hastigheten på menteberegningen for en kjede med fulladdere ved å beregne menten (carry) gruppesvis?
Carry-Lookahead Adder Compute C out for k-bit blocks using generate and propagate signals Some definitions: Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out Generate: Column i will generate a carry out if A i and B i are both 1. G i = A i B i Propagate: Column i will propagate a carry in to the carry out if A i or B i is 1. P i = A i + B i Carry out: The carry out of column i (C i ) is: C i = G i + P i C i-1 = A i B i + (A i + B i )C i-1 Ai Bi Gi Ai Bi Pi Pi Ci-1 Gi Ci Chapter 5 <10>
Block Propagate and Generate Now use column Propagate and Generate signals to compute Block Propagate and Generate signals for k-bit blocks, i.e.: Compute if a k-bit group will propagate a carry in (to the block) to the carry out (of the block) Compute if a k-bit group will generate a carry out (of the block) Example: Block propagate and generate signals for 4-bit blocks (P 3:0 and G 3:0 ): Generally, P 3:0 = P 3 P 2 P 1 P 0 G 3:0 = G 3 + P 3 (G 2 + P 2 (G 1 + P 1 G 0 ) P i:j = P i P i-1 P i-2 P j G i:j = G i + P i (G i-1 + P i-1 (G j+1 + P j+1 G j ) C i = G i:j + P i:j C j-1 Chapter 5 <11>
32-bit CLA with 4-bit Blocks Step 1: Compute G i and P i for all columns C out 4-bit CLA Block C 27 4-bit CLA Block C 23 C 7 4-bit CLA Block C 3 4-bit CLA Block C in Step 2: Compute G and P for k-bit blocks S 31:28 S 27:24 S 7:4 S 3:0 Step 3: C in propagates through each k-bit propagate/generate logic (meanwhile computing sums) Step 4: Compute sum for most significant k-bit block C out B 3 A 3 + S 3 G 3:0 C in C 2 B 2 A 2 + S 2 C 1 B 1 A 1 + S 1 P 3:0 C 0 B 0 + S 0 A 0 C in G 3 P 3 G 2 P 2 G 1 P 1 G 0 P 3 P 2 P 1 P 0 A 31:28 B 31:28 A 27:24 B 27:24 B 7:4 A 7:4 B 3:0 A 3:0 Chapter 5 <12>
Carry-Lookahead Adder Delay For N-bit CLA with k-bit blocks: t CLA = t pg + t pg_block + ( N k 1)t AND_OR + kt FA t pg : delay to generate all P i, G i (1 gate delay) t pg_block : delay to generate all P i:j, G i:j (simultaneous for all blocks) t AND_OR : delay from C in to C out of final AND/OR gate in k-bit CLA block ( 2 gate delays * (number of blocks 1) ) kt FA : delay induced by full adders in one block An N-bit carry-lookahead adder is generally much faster than a ripple-carry adder for N > 16 Chapter 5 <13>
Carry-Lookahead Adder Delay For N-bit CLA with k-bit blocks: t CLA = t pg + t pg_block + ( N k 1)t AND_OR + kt FA t pg : delay to generate all P i, G i (1 gate delay) t pg_block : delay to generate all P i:j, G i:j (simultaneous for all blocks) t AND_OR : delay from C in to C out of final AND/OR gate in k-bit CLA block ( 2 gate delays * (number of blocks 1) ) kt FA : delay induced by full adders in one block An N-bit carry-lookahead adder is generally much faster than a ripple-carry adder for N > 16 MERK: bare «AND_OR» leddet må multipliseres med antall blokker Chapter 5 <14>
A0 B0 Critical path CLA N= 32 (bit), k = 4 (bit per block) pg_block0 G0 P0 tpg Merk: Resultatet slik det er satt opp her blir ikke 100% likt boka, men det skalerer likt. DVS: Her: tpg + tpg_block + (N/k-1)tAND_OR + ktfa - tand = tpg_block og tfa kan være 2 gate delay, boka bruker 3. P3:0 AND_OR0 Cin (N/k - 1)tAND_OR AND_OR6 C31 (overflow) S31 + + + + ktfa
Prefiks adder? Ripple carry skalerer med N CLA skalerer med N/k + k.. Kan vi oppnå logn ved å regne ut generate på en annen måte? 16
Prefix Adder Computes carry in (C i-1 ) for each column, then computes sum: S i = (A i B i ) C i Computes G and P for 1-, 2-, 4-, 8-bit blocks, etc. until all G i (carry in) known log 2 N stages Chapter 5 <17>
Prefix Adder Carry in either generated in a column or propagated from a previous column. Column -1 holds C in, so G -1 = C in, P -1 = 0 Carry in to column i = carry out of column i-1: C i-1 = G i-1:-1 G i-1:-1 : generate signal spanning columns i-1 to -1 Sum equation: S i = (A i B i ) G i-1:-1 Goal: Quickly compute G 0:-1, G 1:-1, G 2:-1, G 3:-1, G 4:-1, G 5:-1, (called prefixes) Chapter 5 <18>
Prefix Adder Generate and propagate signals for a block spanning bits i:j G i:j = G i:k + P i:k G k-1:j P i:j = P i:k P k-1:j In words: Generate: block i:j will generate a carry if: upper part (i:k) generates a carry or upper part (i:k) propagates a carry generated in lower part (k-1:j) Propagate: block i:j will propagate a carry if both the upper and lower parts propagate the carry Chapter 5 <19>
16-Bit Prefix Adder Schematic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0-1 Antall steg = Log 2 ant. bit + 2 14:13 12:11 14:11 13:11 10:9 10:7 9:7 8:7 6:5 6:3 5:3 4:3 2:1 2:-1 1:-1 0:-1 DVS Propagation Delay = t (and el or) + t and + t or Log 2 (ant. bit) + 2t xor 14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1 Hvis t port = t and = t or = t xor 15 14:-1 13:-1 12:-1 11:-1 14 13 12 11 10:-1 9:-1 8:-1 7:-1 10 9 8 7 6 5 4 3 2 1 0 Får vi propagation delay = 3t port + 2t port Log 2 ant. bit = Legend i i:j i t port (3 + 2Log 2 ant. bit ) B i A i P i:k P k-1:j G i:k G k-1:j B i G i-1:-1 A i Her: ant.bit = 16 => delay = t port 3 + 2 4 = 11t port P i:i G i:i P i:j G i:j S i Portkombinasjoner kan i noen tilfeller kombineres på transistornivå, slik at en «seriekobling» av to porter ikke nødvendigvis gir dobbelt delay. (ref 3input XOR = t XOR på neste slide) Chapter 5 <20>
Prefix Adder Delay t PA = t pg + log 2 N(t pg_prefix ) + t XOR t pg : delay to produce P i, G i (AND or OR gate) t pg_prefix : delay of black prefix cell (AND-OR gate) Chapter 5 <21>
Adder Delay Comparisons Compare delay of: 32-bit ripple-carry, CLA, and prefix adders CLA has 4-bit blocks k = 4 2-input gate delay, t pg = 100 ps full adder delay, t FA = 300 ps t ripple = Nt FA = 32(300 ps) = 9.6 ns t CLA t PA = t pg + t pg_block + (N/k 1)t AND_OR + kt FA = [100 + 600 + (7)200 + 4(300)] ps = 3.3 ns = t pg + log 2 N(t pg_prefix ) + t XOR = [100 + log 2 32(200) + 100] ps = 1.2 ns Chapter 5 <22>
Subtracter Symbol A B N N - Y N Implementation A N + Y N B Hvordan lager vi N to-kompliments tall..? N Chapter 5 <23>
Subtracter, A-B Symbol A B N N - Y N Implementation A B N N N + Y N Chapter 5 <24>
Comparator: Equality Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A 1 Equal Equal B 1 A 0 B 0 Chapter 5 <25>
Comparator: Less Than A N B N Eks: 5-3, og 3-5 som 4 bit to-komplement 5 = "0101", -5 = "1010" + 1 = "1011" 3 = "0011", -3 = "1100" + 1 = "1101" - N A-B 5-3: A-B 3-5: [N-1] A < B 0101 + 1101 =10010 A<B = 0, false 0011 + 1011 =01110 A<B = 1, true Chapter 5 <26> 5-<26>
ALU: Arithmetic Logic Unit ALU should perform: Addition Subtraction AND OR Chapter 5 <27>
ALU: Arithmetic Logic Unit ALUControl 1:0 Function 00 Add 01 Subtract 10 AND 11 OR Example: Perform A + B ALUControl = 00 Result = A + B Chapter 5 <28>
ALU: Arithmetic Logic Unit ALUControl 1:0 Function 00 Add 01 Subtract 10 AND 11 OR Example: Perform A OR B ALUControl 1:0 = 11 Mux selects output of OR gate as Result, so Result = A OR B Chapter 5 <29>
ALU: Arithmetic Logic Unit ALUControl 1:0 Function 00 Add 01 Subtract 10 AND 11 OR Example: Perform A + B ALUControl 1:0 = 00 ALUControl 0 = 0, so: Cin to adder = 0 2 nd input to adder is B Mux selects Sum as Result, so Result = A + B Chapter 5 <30>
ALU with Status Flags Flag Description N Z C V Result is Negative Result is Zero Adder produces Carry out Adder overflowed Chapter 5 <31>
ALU with Status Flags Chapter 5 <32>
ALU with Status Flags: Negative N = 1 if: Result is negative So, N is connected to most significant bit of Result Chapter 5 <33>
ALU with Status Flags: Zero Z = 1 if: all of the bits of Result are 0 Chapter 5 <34>
ALU with Status Flags: Carry C = 1 if: C out of Adder is 1 AND ALU is adding or subtracting (ALUControl is 00 or 01) Chapter 5 <35>
ALU with Status Flags: overflow V = 1 if: The addition of 2 samesigned numbers produces a result with the opposite sign Chapter 5 <36>
ALU with Status Flags: overflow V = 1 if: ALU is performing addition or subtraction (ALUControl 1 = 0) Chapter 5 <37>
ALU with Status Flags: overflow V = 1 if: ALU is performing addition or subtraction (ALUControl 1 = 0) AND A and Sum have opposite signs Chapter 5 <38>
ALU with Status Flags: overflow V = 1 if: ALU is performing addition or subtraction (ALUControl 1 = 0) AND A and Sum have opposite signs AND A and B have same signs upon addition OR A and B have different signs upon subtraction Chapter 5 <39>
ALU with Status Flags: overflow V = 1 if: ALU is performing addition or subtraction (ALUControl 1 = 0) AND A and Sum have opposite signs AND A and B have same signs upon addition (ALUControl 0 = 0) OR A and B have different signs upon subtraction (ALUControl 0 = 1) Chapter 5 <40>
ALU with Status Flags Chapter 5 <41>
Shifters, definition Logical shifter: shifts value to left or right and fills empty spaces with 0 s Ex: 11001 >> 2 = Ex: 11001 << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb) (signed 2 n, /2 n ) Ex: 11001 >>> 2 = Ex: 11001 <<< 2 = 00110 00100 11110 00100 VHDL ("11001" srl 2) ("11001" sll 2) ("11001" sra 2) ("11001" sla 2) Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: 11001 ROR 2 = Ex: 11001 ROL 2 = 01110 00111 ("11001" ror 2) ("11001" rol 2) Copyright 2007 Chapter 5 <42> 5-<42>
Shifter Design A 3 A 2 A 1 A 0 shamt 1:0 2 00 S 1:0 01 10 Y 3 shamt 1:0 A 3:0 >> Y 3:0 2 4 4 00 01 10 11 S 1:0 Y 2 11 00 01 S 1:0 10 Y 1 11 00 01 S 1:0 10 Y 0 Shamt = Shift amount, ARM lingo 11 Chapter 5 <43>
Shifters as Multipliers, Dividers A << N = A 2 N Example: 00001 << 2 = 00100 (1 2 2 = 4) Example: 11101 << 2 = 10100 (-3 2 2 = -12) A >>> N = A 2 N Example: 01000 >>> 2 = 00010 (8 2 2 = 2) Example: 10000 >>> 2 = 11100 (-16 2 2 = -4) Chapter 5 <44>
Multipliers Partial products formed by multiplying a single digit of the multiplier with multiplicand Shifted partial products summed to form result Decimal Binary 230 x 42 460 + 920 9660 multiplicand multiplier partial products result 0101 x 0111 0101 0101 0101 + 0000 0100011 230 x 42 = 9660 5 x 7 = 35 Chapter 5 <45>
4 x 4 Multiplier A B 4 x 4 P B 0 B 1 8 A 3 A 2 A 1 A 0 0 A 3 A 2 A 1 A 0 0 x B 3 B 2 B 1 B 0 B 2 A 3 B 0 A 2 B 0 A 1 B 0 A 0 B 0 A 3 B 1 A 2 B 1 A 1 B 1 A 0 B 1 0 A 3 B 2 A 2 B 2 A 1 B 2 A 0 B 2 B 3 + A 3 B 3 A 2 B 3 A 1 B 3 A 0 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 0 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 Chapter 5 <46>
Counters Symbol Implementation Increments on each clock edge Used to cycle through numbers. For example, 000, 001, 010, 011, 100, 101, 110, 111, 000, 001 Example uses: Digital clock displays Program counter: keeps track of current instruction executing CLK Q Reset N 1 N N + N CLK r Reset generic (N : positive := 8); --- count : out std_logic_vector (N-1 downto 0); --- COUNTER : process(reset, clk) begin if (reset = 1 ) then count <= (others => 0 ); elsif rising_edge(clk) then count <= std_logic_vector( unsigned(count) + 1 ); end if; end process COUNTER; N Q Chapter 5 <47>
Shift Registers (not shifters) Shift a new bit in on each clock edge Shift a bit out on each clock edge Serial-to-parallel converter: converts serial input (S in ) to parallel output (Q 0:N-1 ) Symbol: Implementation: CLK Q N S in S out S in S out Q 0 Q 1 Q 2 Q N-1 Chapter 5 <48>
Shift Register with Parallel Load When Load = 1, acts as a normal N-bit register When Load = 0, acts as a shift register Now can act as a serial-to-parallel converter (S in to Q 0:N-1 ) or a parallel-to-serial converter (D 0:N-1 to S out ) Load Clk S in D 0 D 1 D 2 D N-1 0 1 0 1 0 1 0 1 S out Q 0 Q 1 Q 2 Q N-1 Chapter 5 <49>
Memory Arrays Efficiently store large amounts of data 3 common types: Dynamic random access memory (DRAM) Static random access memory (SRAM) Read only memory (ROM) M-bit data value read/ written at each unique N-bit address Address N Array M Data Chapter 5 <50>
Memory Arrays 2-dimensional array of bit cells Each bit cell stores one bit N address bits and M data bits: Address N Array 2 N rows and M columns Depth: number of rows (number of words = 2 N ) M Width: number of columns (size of word) Data Address Data Array size: depth width = 2 N M Address 2 Array 11 10 01 0 1 0 1 0 0 1 1 0 depth 3 00 0 1 1 Data width Chapter 5 <51>
Memory Array Example 2 2 3-bit array Number of words: 4 Word size: 3-bits For example, the 3-bit word at address 10 is 100 Address Data Address 2 Array 11 10 01 0 1 0 1 0 0 1 1 0 depth 3 00 0 1 1 Data width Chapter 5 <52>
Memory Array Bit Cells wordline bit bitline wordline = 1 bit = 0 bitline = 0 wordline = 0 bit = 0 bitline = Z wordline = 1 bit = 1 bitline = 1 wordline = 0 bit = 1 bitline = Z (a) (b) Chapter 5 <53>
Memory Array Wordline: like an enable single row in memory array read/written corresponds to unique address only one wordline HIGH at once Dekoder gir kun én linje høy av gangen! 2:4 Decoder bitline 2 bitline 1 bitline 0 11 wordline 3 Address 2 10 wordline 2 bit = 0 bit = 1 bit = 0 01 wordline 1 bit = 1 bit = 0 bit = 0 00 wordline 0 bit = 1 bit = 0 bit = 1 bit = 1 bit = 0 bit = 1 Data 2 Data 1 Data 0 Chapter 5 <54>
Multi-ported Memories Port: address/data pair 3-ported memory 2 read ports (A1/RD1, A2/RD2) 1 write port (A3/WD3, WE3 enables writing) Register file: small multi-ported memory CLK WE3 A1 RD1 N M A2 RD2 N M Multiported betyr at man kan lese og eller skrive til flere adresser samtidig. N M A3 WD3 Array Chapter 5 <55>
Types of Memory Random access memory (RAM): volatile Read only memory (ROM): nonvolatile Chapter 5 <56>
RAM: Random Access Memory Volatile: loses its data when power off Read and written quickly Main memory in your computer is RAM (DRAM) Historically called random access memory because any data word accessed as easily as any other (in contrast to sequential access memories such as a tape recorder) Chapter 5 <57>
Types of RAM DRAM (Dynamic random access memory) SRAM (Static random access memory) Differ in how they store data: DRAM uses a capacitor SRAM uses cross-coupled inverters Chapter 5 <58>
Robert Dennard, 1932 - Invented DRAM in 1966 at IBM Others were skeptical that the idea would work By the mid-1970 s DRAM in virtually all computers Kilde bilde: Fred Holland, Wikipedia Lisens: Creative Commons Attribution-Share Alike 3.0 Unported Chapter 5 <59>
DRAM Data bits on capacitor Dynamic because the value needs to be refreshed (rewritten) periodically and after read: Charge leakage from the capacitor degrades the value Reading destroys the value bitline bitline wordline bit wordline bit Chapter 5 <60>
DRAM wordline bitline wordline bitline bit = 1 + + bit = 0 Chapter 5 <61>
SRAM wordline wordline bitline bit bitline bitline SRAM vs DRAM: Raskere Tar større fysisk plass Bruker lite strøm til å vedlikeholde verdier Chapter 5 <62>
ROM: Read Only Memory Nonvolatile: retains data when power off ROM bit cell: Read quickly, but writing is impossible or slow Flash memory in cameras, thumb drives, and digital cameras are all ROMs Historically called read only memory because ROMs were written at manufacturing time or by burning fuses. Once ROM was configured, it could not be written again. This is no longer the case for Flash memory and other types of ROMs. Bitline is being pulled high weakly (VHDL: H ), and forced low by intact fuse Chapter 5 <63>
Fujio Masuoka, 1944 - Developed memories and high speed circuits at Toshiba, 1971-1994 Invented Flash memory as an unauthorized project pursued during nights and weekends in the late 1970 s The process of erasing the memory reminded him of the flash of a camera Toshiba slow to commercialize the idea; Intel was first to market in 1988 Flash has grown into a $25 billion per year market Chapter 5 <64>
Flash prinsippskisse (digresjon, ikke pensum) MOSFET type transistor Source line er jordet ( 0 ). Bitline har pullup og er i utgangspunktet 1 (vises ikke) FloatGate (FG) er i utgangspunktet flytende (isolert), kan holde ladning nærmest ubegrenset lenge Svak positiv spenning på wordline gjør transistoren ledende hvis det ikke er lagret elektroner i FG Ie vi får 0 ved ledning, 1 ellers. Elektroner kan lagres på FG ved å kjøre både bitline og wordline (tilstrekkelig) lav (tunnelering) Elektroner kan fjernes på FG ved å benytte tilstrekkelig høy spenning (tunnelering) på Word Line («Flasher» hele ordet til «0») https://en.wikipedia.org/wiki/flash_memory
ROM: Dot Notation 2:4 Decoder 11 wordline bitline Address 2 10 bit cell containing 0 01 bitline 00 Data 2 Data 1 Data 0 wordline bit cell containing 1 Chapter 5 <66>
ROM Storage Address 2 2:4 Decoder 11 10 01 Address 11 10 01 Data 0 1 0 1 0 0 1 1 0 depth 00 00 0 1 1 Data 2 Data 1 Data 0 width Chapter 5 <67>
Memory Arrays Review 2:4 Decoder bitline 2 bitline 1 bitline 0 Address 2 11 10 01 00 wordline 3 wordline 2 wordline 1 wordline 0 bit = 0 bit = 1 bit = 1 bit = 0 bit = 1 bit = 0 bit = 1 bit = 1 bit = 0 bit = 0 bit = 0 bit = 1 ROM bit cell: wordline DRAM bit cell: bitline Data 2 Data 1 Data 0 SRAM bit cell: bitline bitline wordline Chapter 5 <68>
ROM Logic Address 2:4 Decoder 11 2 Data 2 = A 1 A 0 10 01 00 Data 1 = A 1 + A 0 Data 0 = A 1 A 0 Data 2 Data 1 Data 0 Chapter 5 <69>
Logic with Any Memory Array 2:4 Decoder bitline 2 bitline 1 bitline 0 Data 2 = A 1 A 0 Data 1 = A 1 + A 0 Data 0 = A 1 A 0 Address 2 11 10 01 00 wordline 3 wordline 2 wordline 1 wordline 0 bit = 0 bit = 1 bit = 1 bit = 0 bit = 1 bit = 0 bit = 1 bit = 1 bit = 0 bit = 0 bit = 0 bit = 1 Data 2 Data 1 Data 0 Chapter 5 <70>
Example: Logic with ROMs Implement the following logic functions using a 2 2 3-bit ROM: X = AB Y = A + B Z = AB A, B 2 2:4 Decoder 11 10 01 00 X Y Z Chapter 5 <71>
Logic with Memory Arrays Implement the following logic functions using a 2 2 3-bit memory array: X = AB Y = A + B Z = A B A, B 2 2:4 Decoder 11 10 01 00 wordline 3 wordline 2 wordline 1 wordline 0 bit = 1 bit = 0 bit = 0 bit = 0 bitline 2 bitline 1 bitline 0 bit = 1 bit = 1 bit = 1 bit = 0 bit = 0 bit = 1 bit = 0 bit = 0 X Y Z Chapter 5 <72>
Logic with Memory Arrays Called lookup tables (LUTs): look up output at each input combination (address) 4-word x 1-bit Array Truth Table A B Y 0 0 0 0 1 0 1 0 0 1 1 1 A B 2:4 Decoder 00 A 1 01 A 0 10 11 bit = 0 bit = 0 bit = 0 bit = 1 bitline Y Chapter 5 <73>
Logic Arrays Programmable Logic PLAs (Programmable logic arrays) AND array followed by OR array Combinational logic only Fixed internal connections FPGAs (Field programmable gate arrays) Array of Logic Elements (LEs) Combinational and sequential logic Programmable internal connections Chapter 5 <74>
PLAs X = ABC + ABC Y = AB Inputs M AND ARRAY Implicants N OR ARRAY A B C P Outputs OR ARRAY ABC ABC AB AND ARRAY X Y Chapter 5 <75>
PLAs: Dot Notation Inputs M AND ARRAY Implicants N OR ARRAY A B C P Outputs OR ARRAY ABC ABC AB AND ARRAY X Y Chapter 5 <76>
FPGA: Field Programmable Gate Array Composed of: LEs (Logic elements): perform logic IOEs (Input/output elements): interface with outside world Programmable interconnection: connect LEs and IOEs Some FPGAs include other building blocks such as multipliers and RAMs Chapter 5 <77>
General FPGA Layout Chapter 5 <78>
LE: Logic Element Composed of: LUTs (lookup tables): perform combinational logic Flip-flops: perform sequential logic Multiplexers: connect LUTs and flip-flops Chapter 5 <79>
Altera Cyclone IV LE Chapter 5 <80>
FPGA Design Flow Using a CAD tool (such as Altera s Quartus II) Enter the design using schematic entry or an HDL Simulate the design Synthesize design and map it onto FPGA Download the configuration onto the FPGA Test the design Chapter 5 <81>
Anbefalte oppgaver Oppgaver 5.1, 5.3, 5.4, 5.8, 5.9, 5.11, 5.13, 5.17, 5.18, 5.19, 5.20, 5.22, 5.25, 5.26, 5.48 Ekstra 5.5, 5.6, 5.7, 5.10, 5.12, 5.14, 5.21, 5.23, 5.24, 5.45, 5.52 82